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| 7 - 1 dc - 18 ghz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier v01.0613 HMC1061LC5 general description features functional diagram the HMC1061LC5 is a sige monolithic, fully differential, dual rank, track-and-hold (t/h) that provides unprecedented bandwidth and dynamic-range performance to wideband sampled signal systems. the t/h offers precision signal sampling over 18 ghz bandwidth, with 9 - 10-bit linearity from dc to beyond 5 ghz input frequency, 1.5 mv noise, and <70 fs random aperture jitter. the device can be clocked to 4 gs/s with minimal dynamic range loss. the t/h can be used to expand the bandwidth and/or high-frequency linearity of high-speed a/d conversion and signal acquisition systems. 18 ghz input bandwidth (1 vp-p full scale) 4 gs/s maximum sampling rate 68 db sfdr (4 ghz / 0.5 vp-p input, clk = 1 gs/s) 56 db sfdr (4 ghz / 1 vp-p input, clk = 1 gs/s) direct-coupled i/o ultra-clean output waveforms, minimal glitching >60 db hold mode feedthrough rejection 1.5 mv rms hold mode output noise rohs compliant 5x5 mm smt package typical applications the HMC1061LC5 is ideal for: ? rf ate applications ? digital sampling oscilloscopes ? rf demodulation systems ? digital receiver systems ? high speed peak detectors ? software defned radio ? radar, ecm & elint systems ? high speed dac de-glitching electrical specifcations t a = +25 c, see test conditions on following page herein. parameter conditions test level min. typ. max. units analog inputs (inp, inn) differential full scale range full-scale input for linearity test 1 1 vpp input resistance each lead to ground 3 50 return loss 0 to 12 ghz 3 -23 db return loss 12 to 18 ghz 3 -8 db input common mode voltage 3 - 0.1 0 0.1 v clock inputs (clkap, clkan, clkbp, clkbn) dc differential clock high voltage 3 20 40 2000 mv dc differential clock low voltage 3 -2000 -40 -20 mv amplitude (sinusoidal input) per port 2 -6 0 10 dbm input common mode voltage 3 -0.5 0 0.5 v clock slew rate recommended for best linearity 3 2 - 4 v/ns return loss 0 to 3 ghz 3 24 db return loss 3 to 6 ghz 3 18 db input resistance each lead to ground 3 50 data converters - s m t 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com
7 - 2 electrical specifcations (continued) parameter conditions test level min. typ. max. units analog outputs (outp, outn) differential full scale range 4 1 vp-p common mode output voltage 4 0 v output impedance per port 3 50 return loss 0 to 5 ghz 3 14 db track mode dynamics baseband gain 1 -2.5 0 1 db track mode bandwidth @ 1 vp-p input 4 tbd ghz integrated noise [2] 3 tbd mv rms hold mode dynamics sampling bandwidth @ -3 db gain, 1 vp-p input level 3 18 ghz differential droop rate (linear component) 1 -1.4 %/ns differential droop rate magnitude (fixed component) 1 4 mv/ns feedthrough rejection @ 3 ghz 3 60 db integrated noise [2] 500 mhz clock frequency 3 1.45 mv rms maximum hold time (1st rank) 3 2 ns maximum hold time (2nd rank) 3 2 ns total maximum effective hold time 3 4 ns single tone thd/sfdr @ 0.995 ghz full scale input (1 vp-p) [1] 3 -54 / 54 db single tone thd/sfdr @ 1.995 ghz full scale input (1 vp-p) [1] 3 -55 / 55 db single tone thd/sfdr @ 2.995 ghz full scale input (1 vp-p) [1] 3 -55 / 55 db single tone thd/sfdr @ 3.995 ghz full scale input (1 vp-p) [1] 1 -55 / 56 db single tone thd/sfdr @ 4.995 ghz full scale input (1 vp-p) [1] 3 -55 / 57 db single tone thd/sfdr @ 5.995 ghz full scale input (1 vp-p) [1] 3 -52 / 54 db single tone thd/sfdr @ 7.995 ghz full scale input (1 vp-p) [1] 3 -43 / 46 db single tone thd/sfdr @ 9.995 ghz full scale input (1 vp-p) [1] 3 -34 / 37 db single tone thd/sfdr @ 11.995 ghz full scale input (1 vp-p) [1] 3 -31 / 33 db single tone thd/sfdr @ 0.995 ghz half full scale input (0.5 vp-p) [1] 3 -65 / 65 db single tone thd/sfdr @ 1.995 ghz half full scale input (0.5 vp-p) [1] 3 -66 / 66 db single tone thd/sfdr @ 2.995 ghz half full scale input (0.5 vp-p) [1] 3 -65 / 66 db single tone thd/sfdr @ 3.995 ghz half full scale input (0.5 vp-p) [1] 3 -66 / 68 db single tone thd/sfdr @ 4.995 ghz half full scale input (0.5 vp-p) [1] 3 -62 / 63 db single tone thd/sfdr @ 5.995 ghz half full scale input (0.5 vp-p) [1] 3 -61 / 61 db single tone thd/sfdr @ 7.995 ghz half full scale input (0.5 vp-p) [1] 3 -51 / 52 db single tone thd/sfdr @ 9.995 ghz half full scale input (0.5 vp-p) [1] 3 -43 / 44 db single tone thd/sfdr @ 11.995 ghz half full scale input (0.5 vp-p) [1] 3 -40 / 42 db track-to-hold & hold-and-track switching aperture delay simulated value -6 ps random aperture jitter full-scale input @ 1 ghz [1] 3 <70 fs differential pedestal (linear component) 1st rank 1 ghz clock frequency, 6 dbm clock power 3 -1.0 % differential pedestal (linear component) 2nd rank 1 ghz clock frequency, 6 dbm clock power 3 0.15 % [1] 1 gs/s clock, clock power = 6 dbm / input terminal. [2] noise bandwidth limited by output amplifer bandwidth of ~7 ghz. HMC1061LC5 v01.0613 dc - 18 ghz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier data converters - s m t 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 7 - 3 test levels 1. 100% production tested at t a = +25 c 2. guaranteed by design/characterization testing 3. characterization sample tested 4. typical value only parameter conditions test level min. typ. max. units differential pedestal magnitude (fixed component) 1st rank 3 2.8 mv differential pedestal magnitude (fixed component) 2nd rank 3 1.6 mv clock frequency @ 50% duty cycle 3 250 4000 mhz clock buffer pipeline delay simulated value 35 ps acquisition time to 1 mv simulated value 132 ps settling time to 1 mv simulated value 135 ps output buffer delay (from 2nd rank hold-node to output) simulated value 43 ps power supply requirements vccth voltage (vccth1 and vccth2) 1.9 2 2.1 v vccth current (sum of vccth1 and vccth2) 1 140 ma vccof voltage (vccof1 and vcc of2) 1.9 2 2.1 v vccof current (sum of vccof1 and vcc of2) 1 47 ma vccob voltage 1.9 2 2.1 v vccob current 1 74 ma vccclk voltage (vccclk1 and vccclk2) 1.9 2 2.1 v vccclk current (sum of vccclk1 and vccclk2) 1 64 ma vee voltage (veeclk1, veeclk2, vee) -5 -4.75 -4.5 v (vee + veeclk) current 1 -357 ma power consumption 1 2.34 w electrical specifcations (continued) HMC1061LC5 v01.0613 dc - 18 ghz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier data converters - s m t 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 7 - 4 sampling transfer function hold-mode sfdr vs. frequency & input power @ f clk = 1 ghz @ +6 dbm hold-mode sfdr vs. frequency & input power @ f clk = 500 mhz @ +10 dbm [1] [2] [1] fs = full-scale input level, hfs = half-full-scale input level [2] the measurement dynamic range for half-full-scale and full-scale inputs is about 68 db and 74 db, respectively, due to measurement noise foor limitations. hence the measured spurious products tend to limit at these levels. hold-mode sfdr vs. frequency & input power @ f clk = 2 ghz @ 0 dbm HMC1061LC5 v01.0613 dc - 18 ghz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier time domain output waveform @ f clk = 500 mhz, f in = 1.125 ghz time domain output waveform @ f clk = 500 mhz, f in = 10.125 ghz -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 0 4000 8000 12000 16000 20000 magnitude(db) frequency(mhz) 3rd order polynomial fit sampling transfer function 30 40 50 60 70 80 024681012 2nd fs sfdr 3rd fs sfdr 2nd hfs sfdr 3rd hfs sfdr sfdr (db) frequency (ghz) 30 40 50 60 70 80 024681012 2nd fs sfdr 3rd fs sfdr 2nd hfs sfdr 3rd hfs sfdr sfdr (db) frequency (ghz) 30 40 50 60 70 80 024681012 2nd fs sfdr 3rd fs sfdr 2nd hfs sfdr 3rd hfs sfdr sfdr (db) frequency (ghz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0246810 differential output voltage (v) time (ns) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0246810 differential output voltage (v) time (ns) track&hold mode track mode data converters - s m t 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 7 - 5 hold-mode sfdr vs. frequency & input power @ f clk = 3 ghz @ 0 dbm hold-mode sfdr vs. frequency & input power @ f clk = 4 ghz @ 0 dbm HMC1061LC5 v01.0613 dc - 18 ghz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier 30 40 50 60 70 80 024681012 2nd fs sfdr 3rd fs sfdr 2nd hfs sfdr 3rd hfs sfdr sfdr (db) frequency (ghz) 30 40 50 60 70 80 024681012 2nd fs sfdr 3rd fs sfdr 2nd hfs sfdr 3rd hfs sfdr sfdr (db) frequency (ghz) data converters - s m t 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 7 - 6 aperture delay: the delay of the exact sample time relative to the time that the hold command is applied to the device. it is the difference between the delay of the clock switching transition to the hold node and the input signal group delay to the hold node. if the input signal group delay to the hold node exceeds the clock delay this quantity can be negative. aperture jitter: the standard deviation of the sample instant in time. acquisition time: the interval between the internal hold-to-track transition and the time at which the hold-node signal is tracking the input signal within a specifed accuracy. it does not include the pipeline delay of the clock buffer. differential pedestal: a component in the sample value caused by charge redistribution in the t/h switch during the sampling transition. in general, the pedestal can consist of three components: a fxed offset, a component that is linearly related to input signal amplitude, and a component that is nonlinearly related to input signal amplitude. the majority of the pedestal is usually linear. the value of the pedestal can be approximated by p = p o + p lin v in where, p o is the fxed pedestal component, p lin is the linear pedestal component, and v in is the sampled signal level. differential droop rate: the slow drift in the differential output voltage of a held sample while the t/h is in hold-mode. it is typically caused by current leakage on the hold capacitors and corresponds to a decay in the held voltage with increasing time. the droop can be approximated as the sum of a fxed component and a component that is linearly related to the held sample voltage. the total droop can be approximated by d = d o + d lin vin where d o is the fxed component, d lin is the linear droop constant and v in is the sampled signal level. the sign of d o tends to be random so only the magnitude is specifed. since the droop is mostly linear, it causes little nonlinearity. feedthrough rejection: a measure of the off-state (hold-mode) isolation of the t/hs internal switch. it is defned as the ratio of the amplitude of the output signal (for a sinusoidal input) feeding through during the hold mode to the amplitude of the output signal during track mode. normalization by the track-mode signal gives the true switch isolation without the effects of the output amplifer bandwidth limiting. full scale range: the voltage range between the minimum and maximum signal levels that can be handled by the t/h while still meeting the specifcations. sampling bandwidth: the -3 db bandwidth of the sampled signal levels represented by the held sample amplitudes. it includes both the bandwidth of the transfer function from the signal input to the hold-node and any band-limiting effects associated with the fnite time duration of the sampling aperture. settling time: the interval between the internal track-hold transition and the time at which the held output signal is settled to within a specifed accuracy. it does not include the pipeline delay of the clock buffer but does include the group delay of the output amplifer. spurious free dynamic range (sfdr): the ratio (usually expressed in db) between the sinusoidal output signal amplitude and the amplitude of the largest non-linearity product falling within one nyquist bandwidth. it may be specifed for both full scale input and some fraction(s) of full scale input. a sfdr based only on 2 nd order nonlinear products is referred to as the 2 nd order sfdr (sfdr2). a sfdr based only on 3 rd order products is referred to as the 3 rd order sfdr (sfdr3). total harmonic distortion (thd): the ratio of the total power in the non-linearity-generated harmonics and harmonic aliases (measured in one nyquist band) to the output signal power. defnition of specifcations HMC1061LC5 v01.0613 dc - 18 ghz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier data converters - s m t 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 7 - 7 application notes general: the HMC1061LC5 ultra-wideband dual rank t/h amplifer is optimized for use in microwave data conversion applications requiring maximum sampling bandwidth, high linearity over a very wide bandwidth, and low noise. a key application of this device is front end sampling for high speed a/d converters to enhance their input bandwidth and/or high frequency linearity. although several high speed a/d converters offer enhanced sample rates, few of them offer input bandwidth beyond a few ghz. in addition, maintenance of good sampling linearity at frequencies beyond the uhf band is technologically challenging and most a/d converters suffer rapidly degraded linearity above 1 or 2 ghz signal frequency. the HMC1061LC5 can address these limitations with its 18 ghz input bandwidth and excellent broadband linearity. once sampling takes place within the t/h, the low bandwidth held output waveform can be processed by an a/d with substantially reduced bandwidth. in addition, a/d converter linearity performance limitations at high input frequencies are also mitigated because the settled waveform is processed with the optimal baseband linearity of the a/d converter. the dual rank t/h is formed from two cascaded single rank t/hs which are clocked 180 degrees out of phase such that while the master th1 is holding, the slave th2 is tracking and vice versa. the resulting output waveform consists of two time segments. the frst segment consists of the th1 hold mode as seen through th2 track mode transfer function. at the beginning of the 2nd time segment, th2 samples the held th1 waveform and then continues to hold that value while th1 switches back to track-mode and reacquires/tracks the input waveform. the resulting output waveform provides a held sample value of nearly one complete clock cycle, thus presenting the downstream a/d converter with a constant, settled waveform with minimal high frequency spectral content. the device can be clocked in one of two ways depending on the voltage applied to the clksel terminal. the device can be confgured such that the slave t/h uses an internal clock derived and buffered from the master clock (clock a). in this case, the clksel terminal should be grounded, the user only needs to provide clock a, and the internal clock 2 driving the slave always operates at the same frequency as the master clock a. alternatively, the clksel terminal can be connected to the vee supply enabling external clock b control of the slave. in this mode, users must supply both clock a and clock b but they have the option of operating the slave at the same or even a different frequency than the master. this mode can be useful for decimation operations (where clock b is a submultiple of the master clock) or other more exotic clocking schemes. in all cases, the maximum hold time limits shown in the table must be followed. esd: on-chip esd protection networks are incorporated on the terminals, but the rf/microwave compatible interfaces provide minimal protection and esd precautions should be used. power supply sequencing: the recommended power supply startup sequence is vccob, vccof, vccth, vccclk, vee / veeclk if biased from independent supplies. vccob, vccof, vccth and vccclk can be connected to one +2 v supply if desired. input signal drive: for best results, the inputs should be driven differentially. the input can be driven single-ended but the linearity of the device will be degraded somewhat. the unused input should be terminated in 50 ohms when driving the device single-ended. clock input: the 1st rank device is in track-mode when (clkap C clkan) is high and it is in hold-mode when (clkap C clkan) is low. the 2nd rank device has an opposite polarity clock. it is in track-mode when (clkbp-clkbn) is low. the clock inputs should be driven differentially if possible. the clock inputs can be driven single-ended if desired but the single-ended amplitude/slew rate should be similar to the full differential amplitude / slew rate recommended for differential drive. the unused input should be terminated in 50 ohms. the t/h-mode linearity of the device varies somewhat with clock power at lower clock frequencies. this results from a weak dependence of the linearity on clock zero crossing slew rate for slew rates beneath a critical value. for optimal linearity, a clock zero-crossing slew rate of roughly 2 - 4 v/ns (per clock input) or more is recommended. for sinusoidal clock inputs, 4 v/ns corresponds to a sinusoidal clock power per differential half-circuit input of -6 dbm at 4 ghz, 0 dbm at 2 ghz, and 6 dbm at 1 ghz. regardless of the clock frequency, a minimum clock amplitude of -6 dbm is recommended (per differential half-circuit input). outputs: the outputs should be sensed differentially for the cleanest output waveforms. the output impedance is 50 ohms resistive returned to the vccob supply. the output stage is designed to drive 50 ohms terminated to ground on each differential half-circuit output. the device offers a true ground-referenced common mode output HMC1061LC5 v01.0613 dc - 18 ghz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier data converters - s m t 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 7 - 8 linearity measurement application notes (continued) when characterizing the linearity of a t/h, the transfer function linearity of the held samples (referred to as t/h-mode linearity) is usually the quantity of most interest to the user. these samples contain the signal information that is ultimately digitized by the downstream a/d converter. a linearity measurement issue unique to the t/h device is the need for output waveform frequency response correction. in the case of a dual rank t/h, the output waveform resembles a square wave with duration equal to the clock period. mathematically, the output can be viewed as the convolution of an ideal delta-function sample train with a single square pulse of duration equal to one clock period. this weights the output spectral content with a sin(f/fs )/(f/fs) (sinc) function frequency response envelope which has nulls at harmonics of the clock frequency fs and substantial response reduction beyond half the clock frequency. this spectral content and envelope function are observed during spectrum analyzer measurement because the analyzer simply reproduces the entire spectrum of the incoming waveform. however, the spectral content of the held samples without the envelope weighting is required for proper measurement of the samples linearity, as would be measured by a downstream a/d converter that samples a time instant in the held waveform. either the impact of the response envelope must be corrected in the data or a measurement method must be used that heterodynes the relevant nonlinear harmonic products to low frequencies to avoid signifcant envelope response weighting. this latter method is referred to as the low frequency beat-product technique. that is usually within 50 mv of ground; however it is possible to adjust the vccob power supply slightly to fne tune the output common-mode level to precisely 0 v if desired. additionally, the common-mode output level may be adjusted within the range of approximately 0.5 v by adjusting the vccob power supply according to the approximate relation vocm=(vccob-2)/2 where vocm is the output common mode voltage and vccob can be varied in the range of +1 v < vccob < +3 v. the bandwidth of the output amplifer that buffers the t/h signal between the hold-node and the 50 ohm outputs is approximately 7 ghz. the broad output buffer bandwidth is maintained to support the fast settling times required for users operating at high clock rates. however, because of the broad bandwidth, the output amplifer noise contribution to the total output noise is signifcant. users operating at lower clock rates (such as < 1 ghz) may optimize their signal-to-noise ratio by fltering the output to a lower bandwidth than the output amplifer bandwidth of 7 ghz. such an output flter will not reduce the sampled front-end noise (which is frozen into the signal samples and represents the majority of the t/h noise because of the wide front-end bandwidth) but it can reduce the output amplifer noise contribution. the user can flter the output to the lowest bandwidth that still retains the maximum settling time required to support the chosen clock rate. typically this optimal bandwidth is of the order of 2 to 3 times the clock rate and it can be realized with a simple single pole rc flter if desired (for example a shunt capacitance on the outputs). for example, a user operating at a clock rate of 350 mhz with a 1 ghz noise bandwidth output flter can achieve approximately 1 db lower noise relative to the unfltered output condition. the output will have very sharp transitions at the clock edges due to the broad output amplifer bandwidth. the user should be aware that any signifcant length of cable between the chip output and the load will cause frequency response roll-off and dispersion that can produce low amplitude tails with relatively long time-constants in the settling of the output waveform into the load. this effect is most noticeable when operating in a lab setting with output cables of a few feet length, even with high quality cable. output cables between the t/h and the load should be of very high quality and 2 ft or less in length. refections between the load and the device will also degrade the hold mode response. the output cable length can be adjusted to minimize the refection perturbations to some extent. in general, the round trip transit time of the cable should be an integer number of clock periods to obtain the minimal refection perturbation in the hold mode portion of the waveform. the optimal performance is obtained when the t/h is within 50 ps or less of the load since this gives a refection duration equal to the approximate settling time of the device. in a/d converter applications the t/h should be placed as close as possible to the a/d converter to minimize refection effects on the path between the t/h output and the input of the a/d converter. HMC1061LC5 v01.0613 dc - 18 ghz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier data converters - s m t 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 7 - 9 linearity measurement (continued) the low frequency beat-product technique is commonly used for high-speed t/h linearity measurements, although the measurement does impose restrictions on the specifc input signal and clock frequencies that can be used. for example, with a clock frequency of 512.5 mhz, a single tone input at 995 mhz beats with the 2nd harmonic of the sampling frequency (through the sampling process) to produce a 1st order beat product at 30 mhz. likewise, the 2nd and 3rd harmonics of the input signal (generated via distortion in the t/h) beat with the 4th and 6th harmonics of the sampling frequency respectively to produce 2nd and 3rd order beat products at 60 mhz and 90 mhz. in this manner, the t/h nonlinearity in the vicinity of 1 ghz can be measured even though the 995 mhz fundamental and the 1.99 ghz and 2.985 ghz nonlinear harmonics are well beyond the 256 mhz 4 db bandwidth of the sinx/x response envelope. the possible input frequency choices are overly limited when the low frequency beat-product technique is used at high clock rates. a related high frequency beat-product measurement utilizing correction for the sinx/x envelope weighting must be employed to measure linearity over a wide range of input frequencies. hittite uses both low frequency and high frequency beat product methods to measure linearity for a wide range of clock and signal frequencies. our high frequency beat-product measurement avoids excessive envelope correction error by maintaining all beat products within the 4 db bandwidth of the sinc function, where the envelope response is well behaved and easily modeled. independent and accurate measurement of linearity in a t/h waveform (without a downstream adc to sample a single point on the held waveform) is challenging at these low nonlinearity levels. this is due to the waveform transitions/ small glitches that can impact the measured spectrum during direct spectrum analyzer measurements of the output waveform (without sampling). these measurement artifacts are worst case at high clock frequencies where a signifcant fraction of the waveform duration is consumed by transients. it is believed that these measurement artifacts at high clock frequencies contribute to the linearity ripple seen in the plots at higher clock rates. the true linearity is likely represented by the average through these curve variations. for the same reasons as described above, we fnd that the linearity characterization of the t/h waveform via direct spectrum analysis tends to represent a worst case scenario relative to the true linearity obtained by sampling one point on the held waveform as would be obtained during t/h-adc measurements. this is supported by our t/h-adc combination measurements documented in our application notes that show substantially better linearity, particularly at low signal frequencies. the measured linearity presented here from direct spectrum analysis of the entire t/h waveform is believed to represent a worst case indication of the true t/h linearity. absolute maximum ratings vccthx, vccofx, vccclkx 2.1 vdc vccob 3 vdc vee, veeclk -5.25 vdc clkap, clkan, clkbp, clkbn input power +10 dbm inp, inn input power +10 dbm junction temperature 125 c continuous pdiss (t= 85 c) 2.5 w thermal resistance (junction to package bottom) 16.0 c/w storage temperature -65 to +150 c operating temperature -40 to +85 c esd sensitivity (hbm) class 1b electrostatic sensitive device observe handling precautions HMC1061LC5 v01.0613 dc - 18 ghz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier data converters - s m t 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 7 - 10 HMC1061LC5 v01.0613 dc - 18 ghz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier outline drawing notes: 1. package body material: alumina 2. lead and paddle plating: 30-80 microinches gold over 50 microinches minimum nickel. 3. dimensions are in inches [millimeters]. 4. lead spacing tolerance is non-cumulative 5. package warp shall not exceed 0.05 mm datum -c- 6. all ground leads must be soldered to pcb rf ground. package base must be soldered to vee plane. 7. classified as moisture sensitivity level (msl) 1. 8. due to the devices power dissipation of 2.34 w, the paddle temperture should be held below 85 c, preferably using vertical thermal conduction to a heat sink. data converters - s m t 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 7 - 11 pin number function description interface schematic 1, 2, 3, 6, 19, 22 gnda analog ground. this ground and clock ground must be connected to the same dc potential but they can be rf-isolated from each other if desired. 4 inp differential signal input (positive) dc-coupled, ground referenced input with nominal common mode level = 0 v input impedance = 50 ohms full-scale differential voltage = 1 vpp maximum input level = +10 dbm 5 inn differential signal input (negative) dc-coupled, ground referenced input with nominal common mode level = 0 v input impedance = 50 ohms full-scale differential voltage = 1 vpp maximum input level = +10 dbm 7, 16 veeclk1 veeclk2 clock buffer vee supplies nominal voltage = -4.75 v (vee+veeclk1+veeclk2) current = -357 ma nominal 8, 17 vccclk1 vccclk2 clock buffer vcc supplies nominal voltage = +2 v (vccclk1+vccclk2) current = 64 ma nominal 9, 12, 15 gndc clock ground. this ground and analog ground must be connected to the same dc potential but they can be rf-isolated from each other. 10, 11 clkan clkap differential clock a input (negative and positive) provides clock to 1st rank device also provides properly timed clock to 2nd rank device when clk_sel = 0 v dc-coupled, ground referenced input with nominal common mode level = 0 v input impedance = 50 ohms 1st rank track mode: differential clock positive 1st rank hold mode: differential clock negative maximum input level = +10 dbm 13, 14 clkbn clkbp differential clock b input (negative and positive) provides clock to 2nd rank device if clk_sel = -4.75 v dc-coupled, ground referenced input with nominal common mode level = 0 v input impedance = 50 ohms terminated if unused 2nd rank track mode: differential clock negative 2nd rank hold mode: differential clock positive maximum input level = +10 dbm 18 clk_select clock mode select terminal nominal 0 v for internal clock b mode, current = 230 a nominal nominal -4.75 v for external clock b mode, current = -230 a nominal pin descriptions HMC1061LC5 v01.0613 dc - 18 ghz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier data converters - s m t 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 7 - 12 HMC1061LC5 v01.0613 dc - 18 ghz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier pin descriptions (continued) pin number function description interface schematic 20, 21 outp, outn differential output (positive and negative) dc-coupled, ground refernced output with nominal common mode level = 0 v output impedance = 50 ohms intended to be dc or ac coupled to 50 ohm load impedance 24, 26, 28, 30, 32, package base vee vee supply nominal voltage = -4.75 v (vee+veeclk1+veeclk2), current = -357 ma nominal 23 vccob vcc supply for the 50 ohm output buffer nominal voltage = +2 v, current = 74 ma nominal can be biased with +1 7 - 14 HMC1061LC5 v01.0613 dc - 18 ghz ultra-wideband, 4 gs/s track-and-hold amplifier application circuit for evaluation pcb data converters - s m t 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com |
Price & Availability of HMC1061LC5
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